1. Field of the Invention
The present invention relates to a failure detection apparatus and a failure detection method for a semiconductor apparatus, and particularly to a failure detection apparatus and a failure detection method for a semiconductor apparatus having a clock and a shield lines.
2. Description of Related Art
As a manufacturing failure of a semiconductor apparatus having IC (Integrated Circuit) and LSI (Large Scale Integration) or the like, a bridge failure due to a short-out between adjacent lines is known. To detect such bridge failure, signals of each adjacent line must be set to inverted values (logical level 0 and 1). Accordingly it is often difficult to detect a failure in general, and thus a method for detecting a bridge failure more efficiently is desired.
A scan test, one of the failure detection methods, is purposed to detect a stack failure in a F/F (flip-flop) and is also able to detect a bridge failure in a CLK (clock) line. However for a F/F not caught in the failure detection, or a CLK line adjacent to a macro not tested, a bridge failure cannot be detected.
For such sections in which a failure therein cannot be detected, conventionally a user pattern is provided to a semiconductor apparatus to detect a failure. However in recent years, there are occasions in which a user pattern cannot be prepared for detecting a failure, and there are increasing number of semiconductor apparatuses that cannot remove manufacturing failure without user patterns provided thereto. Accordingly it is necessary to detect a bridge failure by a different method other than a scan test or a user pattern.
For example a conventional failure detection method for detecting a bridge failure is disclosed in Japanese Unexamined Patent Application Publication No. HEI 5-264676. The flowchart of FIG. 5 illustrates the conventional failure detection method disclosed in Japanese Unexamined Patent Application Publication No. HEI 5-264676.
As shown in FIG. 5, in the conventional failure detection method, a combination of lines between devices which possibly have bridge failures is extracted from a layout pattern of a semiconductor apparatus (S901). Next, a logical pattern is obtained, where the logical pattern makes the extracted line pattern to be logical values 0 and 1 (S902). Then, the obtained logical pattern is input to the semiconductor apparatus to measure static current consumption flowing from a power supply (S903). After that, the measured static current consumption value is compared with a static current consumption value in a normal time that is obtained previously (S904). If the measured static current consumption is found to be larger than the normal time as result of the comparison, a generation of a bridge failure is detected.
However in the conventional failure detection method, a combination of lines connecting each devices is extracted as adjacent lines from a layout pattern, and there was no consideration over a bridge failure between a CLK and a shield lines. Accordingly in the conventional failure detection method, it has now been discovered that a bridge failure between a CLK and shield lines cannot be found for portions where a scan test cannot be used to detect a failure.